Development of a General Purpose Power System Control Board*

In an effort to control modern solid state power modules, a general purpose, multi function power system control board (PSCB) has been under development as a collaboration project between Pohang Accelerator Laboratory (PAL), Korea, and Stanford Linear Accelerator Centre (SLAC), USA. The PSCB is an embedded, interlock supervisory, diagnostic, timing, and set-point control board. It is designed to use in various power systems such as sequenced kicker pulsers, solid state RF modulators, simple DC magnet power supplies, etc. The PSCB has the Ethernet communication with the TCP/IP Modbus protocol. INTRODUCTION As high frequency switching solid state devices are replacing tube devices and linear devices, power systems become more compact and modular. In order to maintain reliable operation of the power system module, the control board is required to have complex diagnostic and control functions. Moreover, the control board needs to be compact and low power consuming to work with a power system module. It also needs to have a fast communication with a main control station. However, there is no such control board available commercially. Therefore, a general purpose power system control board (PSCB) has been under development as a collaboration effort between PAL and SLAC. Fast and slow signal diagnostic functions are specially emphasized in the PSCB. Several PSCB prototypes are fabricated and tested in PAL. MAJOR SPECIFICATIONS The PSCB is a multi-function diagnostic controller. Main specifications and functions of the PSCB are listed in the table 1. As listed in the table, the PSCB has multiple control inputs such as remote gate trigger synchronization, slow and fast ADCs, tandem and external interlock inputs, and various serial communication ports. Main communication of the PSCB is the Modbus TCP/IP UTP Ethernet serial communication. The PSCB has a mutual communication monitor. The PSCB has various control input and output commands such as trigger initialize, trigger start, stop, and reset, stored RAM data reading, arrangement register writing, diagnostic register reading, relay on and off control, digital analog conversion control, etc. Table 1: Major Specification of PSCB INPUT Fast Signal 8 Channel (CH) ADC; 20 MSample/s, 10 MHz bandwidth; Pulse signal with ± 1V max. level, 50Ω impedance, 2mS max. width; Memory size: 512kB/CH x 8-CH = 4096kB Slow Signal 8-CH ADC with a multiplexer; 1Msps sampling speed; Signals with 0~10V level, 1kΩ impedance; Memory size: 512kB Digital 19-CH (9-CH Optocoupler isolated and 10-CH nonisolated TTL); Tandem Interlock input TIMING Remote Gate Trigger Sync. 1-CH remote gate trigger synchronization signal input; Optical fiber receiver input; Frequency: 1 to 150 Hz; Pulse Width and Delay: Adjustable from 1 μS to 2ms with 10ns adjustable step resolution. Clock 100 MHz FPGA clock COMMUNICATION Ethernet Modbus TCP/IP UTP Ethernet; serial RS232C Serial JTAG Serial OUTPUT Digital 10-CH (3-CH Optocoupler isolated and 7-CH nonisolated TTL); Tandem Interlock output DAC 8-CH; 16-bit; Bipolar; ± 10V level output STRUCTURE A block diagram of the PSCB is shown in Fig. 1. In Fig. 1, all inputs and outputs listed in Table 1 are shown. The fast and slow analog signal inputs are connected into differential input operational amplifier circuits in order to minimize common mode signal noise level. Digital inputs and outputs are optocoupler isolated. The 8-ch DAC are not isolated outputs. The PSCB uses a DSP and a FPGA. It uses SRAMs for data storage. The major function of the DSP is communication while the FPGA is used for high speed signal processing. Figure 1: Block diagram of PSCB ___________________________________________ * Work is partly supported by PAL (Pohang Accelerator Laboratory) and by the U.S. Department of Energy under contract DE-AC0276SF00515. [email protected] SLAC-PUB-12683 Contributed to 10th European Particle Accelerator Conference (EPAC 06), 06/26/2006--6/30/2006, Edinburgh, Scotland Major Components In the following, major components of the PSCB are listed; DSP: Analog device-ADSP_BF_533 × 1, with μC linux operating system FPGA: Xilinx Spartan3 _ XC3S1500FG676 × 1 Fast ADC: Analog Device AD9238 × 8 Slow ADC: Analog Device AD7908 × 1 DAC: Burr-Brown DAC7664 × 2 Important properties of the PSCB PCB are PCB size : 270mm * 140mm +48V Single External power source Total power consumption of about 15 W. Built in On-Board DC/DC converter Single ground PCB Local Gate Trigger Synchronization In order to synchronize in time between multiple power modules by a remote gate external trigger synchronization signal, a 100 MHz internal clock is used. A conceptual timing diagram is shown in Fig. 2. Figure 2: Conceptual trigger timing diagram Figure 3 Example of Gate Trigger Synchronization Ch1: Ext_trigger; Ch2: T1_sync_internal; Ch4: Delay_out (Delay: 2 μs, Width: 2 μs) As the remote gate synchronization signal is received in the PSCB as an asynchronous signal (time t0 in Fig. 2), it will immediately generate an internal signal (T1_Sync_internal in Fig.2) that is synchronized with the FPGA clock at the rising edge as shown in Fig. 2 (time t1 in Fig. 2). Then the PSCB will generate a trigger output signal whose delay and pulse width is determined by an operator’s command. The delay and width control resolution is 10 ns. The trigger output is one of the digital outputs of the PSCB. It is aimed to provide as a trigger signal to an IGBT driver circuit. Real scope waveforms of those three are shown in Fig. 3. The output displayed in Ch 4 is a result of 2 μs delay and 2 μs width commands. Signal ADC In Fig. 4, a block diagram of the fast ADC structure is shown. The fast ADC has total 8 channels. The maximum input level of the fast ADC is ±1V. A SMA connector is used for the input. The signal is firstly inputted into a differential operational amplifier. A detail circuit diagram of one fast ADC channel is given in Fig. 5. The signal is converted into a 0 to 1 V level and then transferred into the ADC. The signal is then digitized as 8-bit data with a 20 MSample/s rate, while the internal clock runs with 100 MHz rate. The digitizing process is controlled by the FPGA. The digitized data are sequentially stored into RAMs. For each channel, 8 current data are stored in the memory. The data is transferred to an external controller data base with pre-programmed fault events or by external commands. The digitizing process is sized during the data transfer. Figure 4: Block diagram of the fast ADC structure. -5VA D? 1N4148 D? 1N4148 +3.3VA